module top_module (
    input clk,
    input resetn,    // active-low synchronous reset
    input [3:1] r,   // request
    output [3:1] g   // grant
	);
	localparam A=2'b00;
	localparam B=2'b01;
	localparam C=2'b11;
	localparam D=2'b10;
	
	reg [1:0]state;
	reg [1:0]next_state;
	
	always@(posedge clk)begin
		if(!resetn)begin
			state<=A;
		end
		else begin
			state<=next_state;
		end
	end
	always@(*)begin
		case(state)
			A:begin
				next_state=(r[1])?B:((r[2])?C:((r[3])?D:A));
			end
			B:begin
				next_state=(r[1])?B:A;
			end
			C:begin
				next_state=(r[2])?C:A;
			end
			D:begin
				next_state=(r[3])?D:A;
			end
		endcase
	end
	assign g[1]=state==B;
	assign g[2]=state==C;
	assign g[3]=state==D;
	
endmodule